1. Field of the Invention
The invention relates to a protection circuit for an integrated circuit, and more particularly to an electrostatic discharge (hereafter, ESD) protection circuit disposed at an input pin of the integrated circuit to prevent the gate oxide of a metal-oxide-semiconductor (hereafter, MOS) device from breakdown caused by ESD stress.
2. Description of Related Art
A MOS device of an integrated circuit having four ends consists of a drain, a gate and a source formed within a body. Generally, the body is the substrate of the MOS device or the well region on the substrate. The drain and source, spaced a lateral distance from each other, are doped diffusion regions which are formed on the substrate or the well region of the substrate by diffusion or ion implantation. The gate, disposed between the source and drain on the substrate, is employed to control a channel between the source and drain. In general, the gate consists of a gate oxide and a gate conductor which are formed by a silicon oxide layer and a polysilicon layer, respectively. The MOS device is widely used as a controlled source and a controller switch with control signals inputted to the gate.
The gate of the MOS device is formed by an extremely thin silicon oxide layer of about several hundred .ANG. in thickness. Since the dielectric breakdown strength of the silicon oxide is about 12.times.10.sup.6 V/cm, a gate oxide layer formed by the silicon oxide can withstand a maximum voltage of several ten volts. For example, a gate oxide layer with 150 .ANG. in thickness can withstand a maximum voltage of 18 V. Accordingly, the breakdown strength of the gate oxide mentioned above is large enough to deal with typical input voltages during normal operation. However, a voltage in excess of the maximum voltage (breakdown voltage) may appear at the input pin of an MOS integrated circuit due to ESD stress. Many sources can cause electrostatic stress, including human contact with the integrated circuit, an interference from operation circumstances, etc. Moreover, because the dimensions of MOS devices continue to shrink, the opportunity for breakdown of the gate oxide layer of the MOS device increases.
Therefore, an ESD protection circuit, disposed between the input pin and the internal circuit of the MOS integrated circuit, is needed to protect the internal circuit from ESD damage caused by an outside sudden high voltage applied to the input pin. Basically, a conduction path to a ground or a power source between the input pin and the internal circuit is provided, so the gate of the MOS device can be protected from damage by means of the conduction path when the outside sudden high voltage is applied to the input pin. Currently, a field device known as a thick oxide device is widely employed to be disposed between an input port and a ground (or power source) The above-mentioned field device differs from general MOS devices in that the field device replaces the thin gate oxide with a field oxide. The field oxide having a thickness of about 0.4.about.1.0 .mu.m is formed by thermal oxidation and is mainly used to define and separate each active region. At present, there are two main field device applications:
The first application employs a field device having a metal gate to attain ESD protection. Referring to FIG. 1, a schematic depiction of an ESD protection circuit for a CMOS integrated circuit is shown. The ESD protection circuit includes a resistor 20, a MOS device 30, and a field device 10, disposed between an input port 2 of the integrated circuit and an input point 4 to which gates of a PMOS 6 and an NMOS 8 are connected. The field device 10 has a gate and a drain connected to each other and mainly provides an ESD path. Generally, the resistor 20 which is formed by an N-type diffusion region on a substrate can delay an ESD stress between the input port 2 and input point 4 to directly protect gates of the PMOS 6 and NMOS 8 from ESD damage. Then the field device 10 is used to attain ESD protection. The MOS device 30 provides a ground path before gates of the PMOS 6 and NMOS 8 and speeds up triggering of the field device 10 to an "on" state to form an ESD path. When an electrostatic current into input port 2 flows to ground through the conducted MOS device 30 from resistor 20, a potential difference will be created on both ends of the resistor 20 such that the gate voltage of the field device 10 can be increased to speed-up triggering of the field device 10 to an "on" state.
Referring to FIG. 2, a cross-sectional view of the field device structure of FIG. 1 is shown. The field device 10 is formed on a P-type substrate 100. An N.sup.+ diffusion region 102 serves as the drain region of the field device 10 which is connected to input port 2 by a metal layer 110. An N.sup.+ diffusion 104 serves as the source region of the field device 10 and is connected to a ground by a metal layer 112. Field oxides 106 are disposed between the drain diffusion region 102 and the source diffusion regions 104. Metal layer 110 over field oxides 106 forms the gate of the field device 10 with a dielectric layer 108 positioned therebetween for electrical insulation. Basically, the field device structure shown in FIG. 2 includes two parallel field devices. The greater the number of parallel field devices, the more effective the ESD protection.
The ESD protection circuit mentioned above has an obvious application drawback. When an ESD stress appears, the field device having a metal gate will induce a sub-critical current to speed-up triggering action of the parasitic bi-carrier transistor to an "on" state for electrostatic discharge. However, an electric field on the gate channel of the field device will limit the ESD induced current on the surface region of the gate channel. Thus, during operation, a hotspot will be produced on the edge of the drain region of the channel. That is, when the ESD induced current is large enough, the conduction structure of the material on which the hotspot is located will be destroyed due to increased temperature.
The second application employs a field device having no metal gate for attaining ESD protection. The circuit is shown in FIG. 3 wherein devices which are the same as those in FIG. 1 are marked with the same reference numerals. The field device 10 of FIG. 1 having a gate structure is replaced by a field device 40 without a gate structure in FIG. 3. Referring to FIG. 4, a cross-sectional view of the field device 40 of FIG. 3 having no gate structure is shown. Similarly, in FIG. 4 which are the same material layers as those in FIG. 2 are marked with the same reference numerals. As shown in FIG. 4, a metal layer 114 does not directly cover field oxide layers 106. Thus, in the ESD path from the metal layer 114 to metal layer 112, the ESD induced current can flow in any region of the substrate 100 between the drain diffusion region 102 and the source diffusion region 104 so that hotspots near the drain region of the channel can be prevented. However, the field device without a gate structure requires a higher voltage to trigger electrostatic discharge. This will result in non-uniform ESD protection.
In summary, the field device mentioned in the first application attains preferred ESD protection, but hotspots will be produced during electrostatic discharge. Although the field device mentioned in the second application can prevent such hotspots, this field device provides non-uniform ESD protection.